Tested and confirmed : it's fixed ! Thank you !

Thank you. The diagram is now OK, but the logic table is still wrong. 2 first columns are |CLR and CLR, but I guess there should be |CLR and CLK. Also, maybe it's me who doesn't understand a thing but the second row of the logic table seems wrong. Text says "cleared instantaneously by going active low on the |CLR pin" so why in the second row the status of the second column (CLR here but I guess it should be CLK) does change the output to Q ? It should be L too no ? Then the second row should not exist at all as it is the same as the first one, isn't it ?

Ok, thank you ! :)

The diagram seems wrong too, it looks like it is the one for the tri-state transceiver

That would be cool !