Cool, but fails to exploit Karnaugh map vs Magnitude comparison. A dual 4way passive MUX and pair of XOR gates can do everything except rotate right, without ripple, and converge to one final result. Faking at the moment cause CRUMB has no 4way passive MUX. Requires dumbing down to a ripple of combinatorial 74HC157 quad 2way MUX. But works to prove 14 logics, 6 magnitude comparisons, A+B, A-B, B-A of either flag polarity. Rotate left through carry by add to self plus carry. Ripple-free prefers 6nS 74CBT3253 with identical pinout to 74HC153, but 250pS 5ohm pass-though. 74LVC2G86 dual XOR is compatible size to fit both on one SSOP to DIP28. Backside SOIC pads are easier to jump than frontside SSOP. This relay drawing better explains how logic vs magnitude yield arithmetic. Standard flags are easy, but no need to wait for Zero at the end of every cycle when magnitude on-demand is available, so omit U4. Note free bidirectional XOR across lamps and coils. Flyback damped by 3mm incandescent "grain-of-wheat" lamps which double as indicators. CBEQ might initialize as either polarity Carry, Borrow, Equal, or control line for logic. SPDT or 2way MUX allows override or invert of the stored flag. Setup time for this C coil is in parallel with other coils, again no ripple. No coil waits on CBEQ after that, but series prefixed throws allow current to propagate and solve at wire speed. Like above, except my Result0 should not have been labeled "Parity". Why my screenshot had to include such an error? Too lazy to fix now. Low parts count should lead to faster simulation. But wait, there's more! (I mean less, slightly) Manchester Carry simplifies addition, but complicates two subtracts and six compares. Would not wire that again. But check out grounded S0 and merged S1, omit two control lines without losing any function another can't fake! Downside is limited to conventional 2's comp flag polarity and a control scheme impossible to explain or memorize, but no worse than 74181. I have given Rotate Right Through Carry some thought and decided just look up in ROM. Not necessary to have RRTC to lookup RRTC. But if I had to wire, might use a pair of 74CBT3257 quad 2way to reverse 01234567<>76543210. Then RLTC using add to self plus Carry. Leave the result reversed, cause we will probably march other bits in same direction. This keeps the CBEQ chain simple and fast. Less capacitive fanout.

Draw it in LTSpice? Otherwise, I don't see how you get there from here anytime soon.

Reset might need to be tied or pulled up? Conflicting inputs also have an order of priority. I don't remember the exact rule, only that there are some. -edit- OK found... Reset is highest priority input for all 555. For NE555, Trigger is higher priority than Threshold. For LM555, Threshold is higher priority than Trigger. https://components101.com/articles/lm555-vs-ne555-timer-ics

A relay of any pole and throw count is not a flipflop. Two relays make a flipflop. Perhaps a latching relay with two coils, or SPDT relay flopped with a transistor could do the same. Flipflops are also not relays. They don't isolate, won't switch analog signals through, and don't recognize XOR across the coil as a means of control.

If you do implement relay: Remember XOR across the coil, inductance, resistance, hold at less than initial current, and switch-like throws that flow in either direction. A visual indicator of mechanical position would be nice too. I'm doing OK with 74HC157 in the meanwhile.

An option for gapless power rails would make layout easier. I know breadboards have traditional gaps between each run of 5 holes, but breadboard PCBs usually have gapless rails.

MSB, Middle, and LSB slices. Different because MSB shows Overflow. LSB hosts control switches. This circuit could be a lot more compact with 74HC153 dual 4Way MUX. If you don't mind using the magnitude comparator chain to invert logic, T00 can be grounded. If you don't mind losing identities and asymmetrical functions, T01 and T10 can be tied together. XOR can fake lost identites. Abusing ADD to invert B restores the lost asymmetrical functions. So really, no functions are lost. Just easier to wire, at cost of more difficult to explain. I wired as 3P2T, one 4way flows backward of the original relay drawing, so there is a spare 1P2T per each MUX. Could be chained to detect A=0 and B=0 if either might be useful. I've grounded those spares for sake of low spaghetti. One mistake I've noticed already: Result 0 might also represent Odd, but definitely not Parity. I notice LED Bloom misbehave and overwash at certain angles. (Win10, Steam, Titan X Pascal)

Parallel capacitors also throw an error without some token of resistance between them.

Alright, seems to be working. I havn't yet tested every function. Questions for dev: Should a lit red LED be casting a dark grey shadow? Also my .cru file doesn't yet appear to be an upload this forum recognizes. Also doesn't work if I drag and drop upon, or associate to the EXE. Disguised as .txt, cru upload does appear to be possible.

Turn pots with mousewheel even better. I own a few MIDI knobs, but everyone has a mouse.

I'm trying this relay ALU today. Abusing 7486 XOR for coils, with 74157 MUX for throws. Actual parts I build with are 74LVC2G86 Dual XOR, and 74CBT3253 Dual 4way MUX. Transmission gates preferred because combinatorial MUX dumb CBEQ to a ripple. U1 may combine with U2 and share MathB. But NXOR remaps to XOR when ADDing. No need to wait for 74181, unless your simulation needs that exact ALU and no other.